1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, e.g., a nonvolatile semiconductor memory device including a memory cell capable of storing a plurality of bits.
2. Description of the Related Art
Recently, demand for large-capacity nonvolatile semiconductor memories has been increasing with the rapid spread of digital cameras, portable audio players, and the like, and NAND flash memories have become widely used as these nonvolatile semiconductor memories. To implement a large-capacity NAND flash memory, a multilevel NAND flash memory that stores a plurality of bits in one memory cell transistor has been proposed.
In the NAND flash memory, data is defined by the threshold voltage of a memory cell transistor. Accordingly, a plurality of threshold voltages are used to store multilevel data. Recently, with advances in the micropatterning of elements, the distance between memory cell transistors has become less. This increases the influence of floating gate capacitance between adjacent memory cell transistors. More specifically, the threshold voltage of a memory cell transistor fluctuates owing to the threshold voltage of an adjacent memory cell transistor to which data is to be written later.
In particular, in a multilevel NAND flash memory for storing two or more bits in one cell, it is necessary to greatly narrow a threshold voltage distribution. Therefore, the fluctuation in threshold voltage degrades the reliability of data recorded in a memory cell transistor.
Also, as a related technique of this kind, a technique that increases the speed of data update in a multilevel NAND flash memory has been disclosed (Japanese Patent Application No. 2006-182254).